1. Field of the Invention
The present invention relates to phase locked loops and, more particularly, to a phase locked loop which settles quickly to a usable condition.
2. Statement of the Problem
Phase locked loops (PLLs) are often used in communications equipment to synthesize the transmit output frequency or channel of the communications equipment. In communication systems in general, the ability to change transmit output frequency rapidly is critical and any delay caused by the settling time of the phase locked loop wastes time that would otherwise be used to transmit data between users of the communication system.
Frequency hopping spread spectrum systems, for example, require the transmitter and receiver to rapidly "hop", in unison, on several operating channels, or different frequencies. In frequency hopping systems the operating frequency changes often, up to several times for each digital bit of transmitted data. Another example is a transceiver that transmits during a first time period and receives during a second time period. Where the transmitter circuit and receiver circuit share a single PLL, the PLL must change output frequencies each time the transceiver switches from transmit to receive. Each time the output frequency changes, the communications equipment must wait until the PLL settles to steady state before data can be reliably transmitted, resulting in reduced data rates. Reduced data rates, in turn, result in poorer quality communication, and fewer customers that can be served by the communications equipment.
Prior phase lock loops require time to lock on to the correct phase before their output frequency is stable enough to use. FIG. 1a illustrates a prior art PLL used for frequency synthesis. PLL 100 has a voltage controlled oscillator (VCO) 109 that generates an output 124 proportional to a voltage input coming from summing circuit 108. Summing circuit 108 combines voltage signals from a digital-to-analog converter (DAC) 114 and from loop filter 106, which will be described in greater detail below.
Loop filter 106 receives an input from an output of phase detector 103. The output of phase detector 103 is a function of the phase difference between two inputs; a first input coming from reference oscillator 101 and a second input provided by feeding back the output 124 of VCO 109 through a divide by N block 111. The output of phase detector 103 can be an analog signal or a pulse width modulated signal. Divide by N block 111 serves to divide the signal on output 124 by an integer N and provide frequency gain for PLL 100 so that the output of VCO 109 can be higher than that of reference oscillator 101. Control logic 112 can provide an input to divide by N block 111 over line 113 to adjust the integer N to provide variable frequency output.
Loop filter 106 determines the response time and bandwidth of PLL 100 and removes noise components from the control voltage applied to VCO 109. To provide a high quality signal on output 124, loop filter 106 should ideally provide PLL 100 with narrow bandwidth. However, a narrow bandwidth increases the time required for PLL 100 to settle during a frequency change.
U.S. Pat. No. 5,175,729 issued to Borras et al. shows a method of decreasing settling time by providing two loop filters 106, one that provides a narrow bandwidth and another that provides a wider bandwidth. The wider bandwidth filter is switched in during a frequency change, and the narrow bandwidth filter switched in once the PLL has approached a steady state. Unfortunately, the process of switching the filters itself generates noise and transients which are a source of settling time delay. Also, the bandwidth provided by loop filter 106 is only one source of settling time delay for PLL 100, and so the circuit of the '729 patent provides only limited improvement.
Another method of reducing settling time in PLL 100 involves pretuning VCO 109 to approximate the desired frequency just prior to the frequency change command to PLL 100. U.S. Pat. No. 4,380,742 issued to Hart and U.S. Pat. No. 4,932,074 issued to McCormick show methods of pretuning VCO 109 using a DAC, such as DAC 114 in FIG. 1a, to provide a voltage to the input of VCO 109 through a summing circuit 108. The voltage provided by DAC 114 reduces the frequency excursion required by PLL 100, and thus reduces time required to settle to a steady state. Control logic 112, which may include a microprocessor, addresses a look-up table 116 over line 111 which provides digital input to DAC 114. The digital data stored in look-up table 116 corresponds to a required voltage output for DAC 114 to produce a desired frequency output from VCO 109. The contents of look-up table 116 are determined by calibrating the system.
Although use of DAC 114 reduces settling time for PLL 100, the values stored in look-up table 116 are fixed at the time of calibration, and are accurate only when PLL 100 operates in an environment similar to that existing at the time of calibration. Also, fixed values in look-up table 116 cannot account for gradual changes in device parameters that accumulate over time. As a result, the output of DAC 114 is only an approximation of the correct voltage to pretune VCO 109, and the PLL circuit must finally tune the output to the correct frequency before it can be used. The settling time of PLL 100 using DAC 114 will vary considerably based on the accuracy of information in look-up table 116. Moreover, even if DAC 114 provides an accurate voltage to VCO 109, a phase error will exist between the reference inputs to phase detector 103. PLL 100 attempts to correct this phase error even when the output frequency is correct, resulting in a finite time delay before PLL 100 can settle to steady state.
FIG. 1b illustrates a simplified timing diagram of a frequency change occurring in the prior art PLL 100 of FIG. 1. PLL 100 is required to switch between frequencies f.sub.1, f.sub.2, and f.sub.3 at predetermined intervals. At time pt.sub.1 DAC 114 is prepared with new digital data to pretune VCO 109 during the frequency hop. At time pt.sub.2 DAC 114 is caused to place the new output voltage as an input to VCO 109. The portion of time that having an X drawn through it between pt.sub.2 and pt.sub.3 in FIG. 1b is the settling time required before the new frequency is usable. Typically, settling time of a prior art PLL 100 is about 500 microseconds. For example, the X in the early portion of the f.sub.2 timeframe indicates that the output of PLL 100 is not sufficiently stable to be used to reliably transmit or receive data. It is also apparent from FIG. 1b that a large portion of each timeframe is wasted while PLL 100 settles. For example, even in a slow frequency hopping system that changes frequency every 10 milliseconds, the settling time is almost 5 percent of the total time available at that frequency. This wasted portion of each time frame reduces the effective bandwidth, resulting in poorer communication quality and fewer people served by the communication equipment using PLL 100.
A need exists, especially in communication environments, for a phase locked loop that settles to a desired frequency without requiring a switched loop filter. A further need exists for a phase locked loop that when signalled to change to a new frequency produces an output frequency that is quickly available for use without waiting for settling to the new frequency.